PIC18LF4331 datasheet(278/392 Pages) MICROCHIP

278 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 278

 2010 Microchip Technology Inc.

FIGURE 23-4:

FSCM TIMING DIAGRAM

23.4.3

FSCM INTERRUPTS IN

POWER-MANAGED MODES

As previously mentioned, entering a power-managed

mode clears the fail-safe condition. By entering a

power-managed mode, the clock multiplexer selects

the clock source selected by the OSCCON register.

Fail-safe monitoring of the power-managed clock

source resumes in the power-managed mode.

If an oscillator failure occurs during power-managed

operation, the subsequent events depend on whether

or not the oscillator failure interrupt is enabled. If

enabled (OSCFIF = 1), code execution will be clocked

by the INTOSC multiplexer. An automatic transition

back to the failed clock source will not occur.

If the interrupt is disabled, the device will not exit the

power-managed mode on oscillator failure. Instead, the

device will continue to operate as before, but clocked

by the INTOSC multiplexer. While in Idle mode, subse-

quent interrupts will cause the CPU to begin executing

instructions while being clocked by the INTOSC

multiplexer. The device will not transition to a different

clock source until the fail-safe condition is cleared.

23.4.4

POR OR WAKE FROM SLEEP

The FSCM is designed to detect oscillator failure at any

point after the device has exited Power-on Reset

(POR) or low-power Sleep mode. When the primary

system clock is EC, RC or INTRC modes, monitoring

can begin immediately following these events.

For oscillator modes involving a crystal or resonator

(HS, HSPLL, LP or XT), the situation is somewhat

different. Since the oscillator may require a start-up

time considerably longer than the FCSM sample clock

time, a false clock failure may be detected. To prevent

this, the internal oscillator block is automatically

configured as the system clock and functions until the

primary clock is stable (the OST and PLL timers have

timed out). This is identical to Two-Speed Start-up

mode. Once the primary clock is stable, the INTRC

returns to its role as the FSCM source.

As noted in Section 23.3.1 “Special Considerations

for Using Two-Speed Start-up”

, it is also possible to

select another clock configuration, and enter an

alternate power-managed mode, while waiting for the

primary system clock to become stable. When the new

powered-managed mode is selected, the primary clock

is disabled.

OSCFIF

CM Output

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

CM Test

Note:

The same logic that prevents false

oscillator failure interrupts on POR or wake

from Sleep will also prevent the detection

of the oscillator’s failure to start at all

following these events. This can be

avoided by monitoring the OSTS bit and

using a timing routine to determine if the

oscillator is taking too long to start. Even

so, no oscillator failure interrupt will be

flagged.

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