PIC18LF4331 datasheet(112/392 Pages) MICROCHIP

112 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 112

 2010 Microchip Technology Inc.

10.6

INTx Pin Interrupts

External interrupts on the INT0, INT1 and INT2 pins are

edge-triggered. If the corresponding INTEDGx bit in the

INTCON2 register is set (= 1), the interrupt is triggered

by a rising edge. If the bit is clear, the trigger is on the

falling edge.

When a valid edge appears on the INTx pin, the corre-

sponding flag bit, INTxIF, is set. This interrupt can be

disabled by clearing the corresponding enable bit,

INTxIE. Before re-enabling the interrupt, the flag bit,

INTxIF, must be cleared in software in the Interrupt

Service Routine.

All external interrupts (INT0, INT1 and INT2) can wake-

up the processor from the Idle or Sleep modes if bit,

INTxIE, was set prior to going into those modes. If the

Global Interrupt Enable bit, GIE, is set, the processor

will branch to the interrupt vector following wake-up.

Interrupt priority for INT1 and INT2 is determined by

the value contained in the Interrupt Priority bits,

INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>).

There is no priority bit associated with INT0. It is

always a high-priority interrupt source.

10.7

TMR0 Interrupt

In 8-bit mode (which is the default), an overflow

(FFh

 00h) in the TMR0 register will set flag bit,

TMR0IF. In 16-bit mode, an overflow (FFFFh

0000h)

in the TMR0H:TMR0L registers will set flag bit,

TMR0IF. The interrupt can be enabled/disabled by

setting/clearing enable bit, TMR0IE (INTCON<5>).

Interrupt priority for Timer0 is determined by the value

contained in the interrupt priority bit, TMR0IP

(INTCON2<2>). See Section 12.0 “Timer0 Module”

for further details.

10.8

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

10.9

Context Saving During Interrupts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the fast return stack. If a fast

return from interrupt is not used (see Section 6.1.3

“Fast Register Stack”

), the user may need to save the

WREG, STATUS and BSR registers on entry to the

Interrupt Service Routine. Depending on the user’s

application, other registers may also need to be saved.

Example 10-1 saves and restores the WREG, STATUS

and BSR registers during an Interrupt Service Routine.

EXAMPLE 10-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

W_TEMP

; W_TEMP is in virtual bank

MOVFF

STATUS, STATUS_TEMP

; STATUS_TEMP located anywhere

MOVFF

BSR, BSR_TEMP

; BSR_TMEP located anywhere

;

; USER ISR CODE

;

MOVFF

BSR_TEMP, BSR

; Restore BSR

MOVF

W_TEMP, W

; Restore WREG

MOVFF

STATUS_TEMP, STATUS

; Restore STATUS

PIC18LF4331 Datasheet(PDF) 112 Page - Microchip Technology

PIC18LF4331 Datasheet(HTML) 112 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL