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PIC18LF4331 Datasheet(PDF) 114 Page - Microchip Technology |
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PIC18LF4331 Datasheet(HTML) 114 Page - Microchip Technology |
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114 / 392 page  PIC18F2331/2431/4331/4431 DS39616D-page 114 2010 Microchip Technology Inc. TABLE 11-1: PORTA I/O SUMMARY Pin Function TRIS Setting I/O I/O Type Description RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input is enabled. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input is enabled. AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not affect digital output. RA2/AN2/VREF-/ CAP1/INDX RA2 0 O DIG LATA<2> data output; not affected by analog input. 1 I TTL PORTA<2> data input. Disabled when analog input is enabled. AN2 1 I ANA A/D Input Channel 2. Default input configuration on POR. VREF- 1 I ANA A/D voltage reference low input. CAP1 1 I ST Input Capture Pin 1. Disabled when analog input is enabled. INDX 1 I ST Quadrature Encoder Interface index input pin. Disabled when analog input is enabled. RA3/AN3/VREF+/ CAP2/QEA RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input is enabled. AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR. VREF+ 1 I ANA A/D voltage reference high input. CAP2 1 I ST Input Capture Pin 2. Disabled when analog input is enabled. QEA 1 I ST Quadrature Encoder Interface Channel A input pin. Disabled when analog input is enabled. RA4/AN4/CAP3/ QEB RA4 0 O DIG LATA<4> data output; not affected by analog input. 1 I ST PORTA<4> data input; disabled when analog input is enabled. AN4 1 I ANA A/D Input Channel 4. Default input configuration on POR. CAP3 1 I ST Input Capture Pin 3. Disabled when analog input is enabled. QEB 1 I ST Quadrature Encoder Interface Channel B input pin. Disabled when analog input is enabled. RA5/AN5/LVDIN RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input is enabled. AN5 1 I ANA A/D Input Channel 5. Default configuration on POR. LVDIN 1 I ANA Low-Voltage Detect external trip point input. OSC2/CLKO/RA6 OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes). CLKO x O DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator modes. RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. 1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. OSC1/CLKI/RA7 OSC1 x I ANA Main oscillator input connection. CLKI x I ANA Main clock input connection. RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes. 1 I TTL PORTA<7> data input. Disabled in external oscillator modes. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). |
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