PIC18LF4331 datasheet(180/392 Pages) MICROCHIP

180 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 180

 2010 Microchip Technology Inc.

18.3.1

FREE-RUNNING MODE

In the Free-Running mode, the PWM Time Base regis-

ters (PTMRL and PTMRH) will begin counting upwards

until the value in the PWM Time Base Period register,

PTPER (PTPERL and PTPERH), is matched. The

PTMR registers will be reset on the following input

clock edge and the time base will continue counting

upwards as long as the PTEN bit remains set.

18.3.2

SINGLE-SHOT MODE

In the Single-Shot mode, the PWM time base will begin

counting upwards when the PTEN bit is set. When the

value in the PTMR register matches the PTPER regis-

ter, the PTMR register will be reset on the following

input clock edge and the PTEN bit will be cleared by the

hardware to halt the time base.

18.3.3

CONTINUOUS UP/DOWN COUNT

MODES

In Continuous Up/Down Count modes, the PWM time

base counts upwards until the value in the PTPER

following input clock edge, the timer counts

downwards. The PTDIR bit in the PTCON1 register is

read-only and indicates the counting direction. The

PTDIR bit is set when the timer counts downwards.

18.3.4

PWM TIME BASE PRESCALER

The input clock to PTMR (FOSC/4) has prescaler

options of 1:1, 1:4, 1:16 or 1:64. These are selected by

control bits, PTCKPS<1:0>, in the PTCON0 register.

The prescaler counter is cleared when any of the

following occurs:

• Write to the PTMR register

• Write to the PTCON (PTCON0 or PTCON1)

• Any device Reset

PWMCON1: PWM CONTROL REGISTER 1

R/W-0

U-0

R/W-0

SEVOPS3

SEVOPS2

SEVOPS1

SEVOPS0

SEVTDIR

—

UDIS

OSYNC

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

SEVOPS<3:0>:

PWM Special Event Trigger Output Postscale Select bits

0000

= 1:1 Postscale

0001

= 1:2 Postscale

1111

= 1:16 Postscale

bit 3

SEVTDIR:

Special Event Trigger Time Base Direction bit

= A Special Event Trigger will occur when the PWM time base is counting downwards

= A Special Event Trigger will occur when the PWM time base is counting upwards

bit 2

Unimplemented:

Read as ‘0’

bit 1

UDIS:

PWM Update Disable bit

= Updates from Duty Cycle and Period Buffer registers are disabled

= Updates from Duty Cycle and Period Buffer registers are enabled

bit 0

OSYNC:

PWM Output Override Synchronization bit

= Output overrides via the OVDCON register are synchronized to the PWM time base

= Output overrides via the OVDCON register are asynchronous

Note:

Since the PWM compare outputs are

driven to the active state when the PWM

time base is counting downwards and

matches the duty cycle value, the PWM

outputs are held inactive during the first

half of the first period of the Continuous

Up/Down Count mode until PTMR begins

to count down from the PTPER value.

Note:

The PTMR register is not cleared when

PTCONx is written.

PIC18LF4331 Datasheet(PDF) 180 Page - Microchip Technology

PIC18LF4331 Datasheet(HTML) 180 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL