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IMX53CEC Datasheet(PDF) 26 Page - Freescale Semiconductor, Inc

Part # IMX53CEC
Description  Applications Processors for Consumer Products
PDF  204 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

IMX53CEC Datasheet(HTML) 26 Page - Freescale Semiconductor, Inc

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i.MX53xD Applications Processors for Consumer Products, Rev. 2
26
Freescale Semiconductor
Electrical Characteristics
•IO Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede
NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is
stabilized. Within this group, the supplies can be powered-up in any order.
•IO Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after
NVCC_CKIH is stable.
•In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator
(default case for i.MX53xD), there are no related restrictions on VDD_REG, as it is used as their
internal regulators power source.
If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage
during the power-up, it is recommended to activate the VDD_REG before or at the same time
with VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that
the 2.5 V VDD_REG supply shut-off output impedance is higher than 1 k
Ω when it is inactive.
•VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered
on after VCC and before NVCC_EMI_DRAM. The sequence should be:
VCC
→VDD_REG →NVCC_EMI_DRAM
•NVCC_EIM_DRAM_2P5 PoP additional power line timing is the same as DVV_REG
•VDDA and VDDAL1 can be powered ON anytime before POR_B, regardless of any other power
signal.
•VDDGP can be powered ON anytime before POR_B, regardless of any other power signal.
•VP and VPH can be powered up together, or anytime after, the VCC. VP and VPH should come
before POR.
•TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This
is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is
powered ON before the other.
NOTE
The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail reaches its working voltage.



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