| Electronic Components Datasheet Search |
|
IMX53CEC Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
IMX53CEC Datasheet(HTML) 41 Page - Freescale Semiconductor, Inc |
|
41 / 204 page ![]() Electrical Characteristics i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 41 4.5.2 LPDDR2 I/O AC Electrical Characteristics The DDR2/LVDDR2 interface mode fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The DDR3 interface mode fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. Table 23 shows the AC parameters for LPDDR2 I/O operating in DDR2 mode. Output Pad Transition Times (Low Drive) tr, tf 15 pF 35 pF —— 4.82/4.5 10.54/9.95 ns Output Pad Slew Rate (Max Drive)1 tps 15 pF 35 pF 0.69/0.78 0.36/0.39 —— V/ns Output Pad Slew Rate (High Drive)1 tps 15 pF 35 pF 0.55/0.62 0.28/0.30 —— V/ns Output Pad Slew Rate (Medium Drive)1 tps 15 pF 35 pF 0.39/0.44 0.19/0.20 —— V/ns Output Pad Slew Rate (Low Drive)1 tps 15 pF 35 pF 0.21/0.22 0.09/0.1 —— V/ns Output Pad di/dt (Max Drive) tdit — — — 70 mA/ns Output Pad di/dt (High Drive) tdit — — — 53 mA/ns Output Pad di/dt (Medium drive) tdit — — — 35 mA/ns Output Pad di/dt (Low drive) tdit — — — 18 mA/ns Input Transition Times2 trm — — — 25 ns 1 tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 2 Hysteresis mode is recommended for inputs with transition time greater than 25 ns. Table 23. LPDDR2 I/O DDR2 mode AC Characteristics1 1 Note that the JEDEC SSTL_18 specification (JESD8-15a) for class II operation supersedes any specification in this document. Parameter Symbol Test Condition Min Typ Max Unit AC input logic high Vih(ac) — Vref+0.25 —— V AC input logic low Vil(ac) —— — Vref-0.25 V AC differential input voltage2 Vid(ac) — 0.5 — OVDD V Input AC differential cross point voltage3 Vix(ac) — Vref – 0.175 —Vref + 0.175 V Output AC differential cross point voltage4 Vox(ac) — Vref – 0.125 —Vref + 0.125 V Single output slew rate tsr At 25 Ω to Vref 0.4 — 2 V/ns Skew between pad rise/fall asymmetry + skew caused by SSN tSKD clk=266Mhz clk=400Mhz —— 0.2 0.1 ns Table 22. GPIO I/O AC Parameters Fast Mode (continued) Parameter Symbol Test Condition Min Typ Max Unit |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |