IMX53CEC datasheet(76/204 Pages) FREESCALE

76 / 204 page

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Electrical Characteristics

4.7.4

Enhanced Secured Digital Host Controller(eSDHCv2/v3) AC timing

This section describes the electrical information of the eSDHCv2/v3, which includes SD/eMMC4.3

(Single Data Rate) timing and eMMC4.4 (Dual Date Rate) timing.

4.7.4.1

SD/eMMC4.3 (Single Data Rate) AC Timing

Figure 36 depicts the timing of SD/eMMC4.3, and Table 50 lists the SD/eMMC4.3 timing characteristics.

Figure 36. SD/eMMC4.3 Timing

Table 50. SD/eMMC4.3 Interface Timing Specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (Low Speed)

fPP

400

kHz

Clock Frequency (SD/SDIO Full Speed/High Speed)

fPP

25/50

MHz

Clock Frequency (MMC Full Speed/High Speed)

fPP

20/52

MHz

Clock Frequency (Identification Mode)

fOD

100

400

kHz

SD2

Clock Low Time

tWL

7—

SD3

Clock High Time

tWH

7—

SD4

Clock Rise Time

tTLH

—3

SD5

Clock Fall Time

tTHL

—3

eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)

SD6

eSDHC Output Delay

tOD

–5

eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)

SD1

SD3

SD5

SD4

SD7

CMD

output from eSDHCv2 to card

DAT1

......

DAT7

DAT0

CMD

input from card to eSDHCv2

DAT1

......

DAT7

DAT0

SCK

SD2

SD8

SD6

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