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IMX53CEC Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

Part # IMX53CEC
Description  Applications Processors for Consumer Products
PDF  204 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

IMX53CEC Datasheet(HTML) 79 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
i.MX53xD Applications Processors for Consumer Products, Rev. 2
Freescale Semiconductor
79
Figure 38. MII Receive Signal Timing Diagram
4.7.5.2
MII Transmit Signal Timing
The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency
of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency.
Table 53 lists MII transmit channel timing parameters. Figure 39 shows MII transmit signal timing
diagram for the values listed in Table 53.
Table 53. MII Transmit Signal Timing
Num
Characteristic1 2
1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
2 Test conditions: 25pF on each output signal.
Min
Max
Unit
M5
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
5
—
ns
M6
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
—
20
ns
M7
FEC_TX_CLK pulse width high
35%
65%
FEC_TX_CLK period
M8
FEC_TX_CLK pulse width low
35%
65%
FEC_TX_CLK period
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M3
M4
M1
M2



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