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IMX53CEC Datasheet(PDF) 78 Page - Freescale Semiconductor, Inc

Part # IMX53CEC
Description  Applications Processors for Consumer Products
PDF  204 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

IMX53CEC Datasheet(HTML) 78 Page - Freescale Semiconductor, Inc

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i.MX53xD Applications Processors for Consumer Products, Rev. 2
78
Freescale Semiconductor
Electrical Characteristics
4.7.5
FEC AC Timing Parameters
This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC
is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver
interface and transceiver function are required to complete the interface to the media. The FEC supports
the 10/100 Mbps MII (18 pins in total) and the 10 Mbps (only 7-wire interface, which uses 7 of the MII
pins), for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see the i.MX53
Reference Manual.
This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.
4.7.5.1
MII Receive Signal Timing
The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must
exceed twice the FEC_RX_CLK frequency. Table 52 lists the MII receive channel signal timing
parameters and Figure 38 shows MII receive signal timings.
.
SD3
eSDHC Input Setup Time
tISU
2.5
—
ns
SD4
eSDHC Input Hold Time
tIH
2.5
—
ns
Table 52. MII Receive Signal Timing
No.
Characteristics1 2
1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.
2 Test conditions: 25pF on each output signal.
Min
Max
Unit
M1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
—
ns
M2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
—
ns
M3
FEC_RX_CLK pulse width high
35%
65%
FEC_RX_CLK period
M4
FEC_RX_CLK pulse width low
35%
65%
FEC_RX_CLK period
Table 51. eMMC4.4 Interface Timing Specification (continued)
ID
Parameter
Symbols
Min
Max
Unit



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