LSM330DLTR datasheet(36/54 Pages) STMICROELECTRONICS

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Registers description

LSM330DL

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Doc ID 022018 Rev 1

The Interrupt 1 source register is a read-only register.

Reading at this address clears the INT1_SRC_A IA bit (and the interrupt signal on the

INT1_A pin) and allows the refreshment of data in the INT1_SRC_A register if the latched

option was chosen.

7.16

INT1_THS_A (32h)

7.17

INT1_DURATION_A (33h)

The D6 - D0 bits set the minimum duration of the Interrupt 1 event to be recognized. The

duration of the steps and maximum values depend on the ODR chosen.

7.18

CLICK_CFG _A (38h)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Table 46.

INT1_SRC_A description

Table 47.

INT1_THS_A register

0(1)

This bit has to be set to ‘0’ for correct operation.

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 48.

INT1_THS_A description

THS6 - THS0

Interrupt 1 threshold. Default value: 000 0000

Table 49.

INT1_DURATION_A register

0(1)

This bit has to be set to ‘0’ for correct operation.

Table 50.

INT1_DURATION_A description

D6 - D0

Duration value. Default value: 000 0000

Table 51.

CLICK_CFG_A register

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