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HT45FM2C Datasheet(PDF) 92 Page - Holtek Semiconductor Inc |
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HT45FM2C Datasheet(HTML) 92 Page - Holtek Semiconductor Inc |
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92 / 171 page ![]() Rev. 1.10 9� �a� �0� �01� Rev. 1.10 9� �a� �0� �01� HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Preliminar� A/D Operation TherearetwowaystoinitiateanA/DConverterconversioncycle,selectedusingtheADSTSbit. ThefirstoftheseistousetheADSTRbitintheADCR0registerusedtostartandresettheA/D converter.Whenthemicrocontrollerprogramsetsthisbitfromlowtohighandthenlowagain, ananalogtodigitalconversioncyclewillbeinitiated.WhentheADSTRbitisbroughtfromlow tohighbutnotlowagain,theEOCBbitintheADCR0registerwillbesethighandtheanalogto digitalconverterwillbereset. ThesecondmethodofinitiatingaconversionistouesethePWMinterruptsignal.Thiscanbe sourcedfromeitherthePWMperiodordutyinterruptsignal,selectedusingthePWISbit.The DLSTRbitcanactivateadelayfunctionwhichinsertsadelaytimebetweentheincomingPWM interruptsignalandtheactualstartoftheA/Dconversionprocess,withtheactualtimebeingsetup usingtheADDLregister.Theactualdelaytimeiscalculatedbytheregistercontentmultipliedbythe systemclockperiod.ThedelaybetweenthePWMinterruptandthestartoftheA/Dconversionis toreducethepossibilityoferroneousanalogsamplesbeingtakenduringthetimeoflargetransient currentswitchingbythemotordrivetransistors.NotethatiftheDLSTRbitselectsnodelaythe ADDLregistermustbeclearedtozeroandvice-versaifthedelayisselected,thenanon-zerovalue mustbeprogrammedintotheADDLregister. TheEOCBbitintheADCR0registerisusedtoindicatewhentheanalogtodigitalconversion processiscomplete.Thisbitwillbeautomaticallysettozerobythemicrocontrolleraftera conversioncyclehasended.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbeset intheinterruptcontrolregister,andiftheinterruptsareenabled,anappropriateinternalinterrupt signalwillbegenerated.ThisA/Dinternalinterruptsignalwilldirecttheprogramflowtothe associatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled, themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithas beenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle. TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosen tobeeitherfSYSorasubdividedversionoffSYS.Thedivisionratiovalueisdeterminedbythe ADCK2~ADCK0bitsintheADCR1register.AlthoughtheA/Dclocksourceisdeterminedby thesystemclocky,fSYS,andbybitsADCK2~ADCK0,therearesomelimitationsonthemaximum A/Dclocksourcespeedthatcanbeselected.AstheminimumvalueofpermissibleA/Dclock period,tADCK,is0.5μs,caremustbetakenforsystemclockfrequenciesequaltoorgreaterthan 4MHz.Forexample,ifthesystemclockoperatesatafrequencyof4MHz,theADCK2~ADCK0bits shouldnotbesetto“000”.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/D clockperiodwhichmayresultininaccurateA/Dconversionvalues.Refertothefollowingtablefor examples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,special caremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod. fSYS A/D Clock Period (tADCK) ADCK2, ADCK1, ADCK0 =000 (fSYS) ADCK2, ADCK1, ADCK0 =001 (fSYS/2) ADCK2, ADCK1, ADCK0 =010 (fSYS/4) ADCK2, ADCK1, ADCK0 =011 (fSYS/8) ADCK2, ADCK1, ADCK0 =100 (fSYS/16) ADCK2, ADCK1, ADCK0 =101 (fSYS/32) ADCK2, ADCK1, ADCK0 =110 (fSYS/64) ADCK2, ADCK1, ADCK0 =111 5�Hz �00ns* 400ns* 800ns 1.6μs 3.2μs 6.4μs 12.8μs Undefined 10�Hz 100ns* �00ns* 400ns* 800ns 1.6μs 3.2μs 6.4μs Undefined �0�Hz 50ns* 100ns* �00ns* 400ns* 800ns 1.6μs 3.2μs Undefined A/D Clock Period Examples Controllingthepoweron/offfunctionoftheA/Dconvertercircuitryisimplementedusingthe ADOFFbitintheADCR0register.ThisbitmustbezerotopowerontheA/Dconverter.Evenifno pinsareselectedforuseasA/DinputsbyclearingthePCR7~PCR0bitsintheANCSR0registerand PCR8intheANCSR1register,iftheADOFFbitiszerothensomepowerwillstillbeconsumed. InpowerconsciousapplicationsitisthereforerecommendedthattheADOFFissethightoreduce powerconsumptionwhentheA/Dconverterfunctionisnotbeingused. |
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