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HT45FM2C Datasheet(PDF) 18 Page - Holtek Semiconductor Inc |
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HT45FM2C Datasheet(HTML) 18 Page - Holtek Semiconductor Inc |
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18 / 171 page ![]() Rev. 1.10 18 �a� �0� �01� Rev. 1.10 19 �a� �0� �01� HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Preliminar� System Architecture Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed totheirinternalsystemarchitecture.Therangeofdevicestakeadvantageoftheusualfeaturesfound withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance. Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction executionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withthe exceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionset operations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement, branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulator andtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectly orindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditional architecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovidea functionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthis devicesuitableforlow-cost,high-volumeproductionforcontrollerapplications. Clocking and Pipelining Themainsystemclock,derivedfromeitheraHIRCorLIRCoscillatorissubdividedintofour internallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthe beginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4 clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleforms oneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive instructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsare effectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructionswherethe contentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasethe instructionwilltakeonemoreinstructioncycletoexecute. Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twomachinecyclesare requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone cycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming sensitiveapplications. Fe tc h In st . ( PC ) Ex ec ut e In st . (P C- 1) Fe tc h In st . (P C+ 1) Ex ec ut e In st . (P C) Fe tc h In st . (P C+ 2) Ex ec ut e In st . (P C+ 1) PC PC +1 PC +2 f SY S (S yst em C lo ck) P has e Cl o ck T1 Pr ogr am C oun te r P has e Cl o ck T2 P has e Cl o ck T3 P has e Cl o ck T4 Pi pe lin in g System Clocking and Pipelining |
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