WM8983GEFLSLASHV datasheet(84/124 Pages) WOLFSON

84 / 124 page

WM8983

Production Data

PD, Rev 4.3, May 2010

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Audio

Interface

Control

MONO

Selects between stereo and mono

device operation:

0 = Stereo device operation

1 = Mono device operation. Data

appears in ‘left’ phase of LRC.

ADCLRSWAP

Controls whether ADC data appears in

‘right’ or ‘left’ phases of LRC clock:

0=ADC left data appear in ‘left’ phase of

LRC and right data in 'right' phase

1=ADC left data appear in ‘right ’ phase

of LRC and right data in 'left' phase

DACLRSWAP

Controls whether DAC data appears in

‘right’ or ‘left’ phases of LRC clock:

0=DAC left data appear in ‘left’ phase of

LRC and right data in 'right' phase

1=DAC left data appear in ‘right’ phase

of LRC and right data in 'left' phase

4:3

FMT

Audio interface Data Format Select:

00=Right Justified

01=Left Justified

10=I

2S format

11= DSP/PCM mode

6:5

Word length

00=16 bits

01=20 bits

10=24 bits

11=32 bits (see note)

LRP

LRC clock polarity

0=normal

1=inverted

BCP

BCLK polarity

0=normal

1=inverted

LOOPBACK

Digital loopback function

0=No loopback

1=Loopback enabled, ADC data output

is fed directly into DAC data input.

Table 55 Audio Interface Control

Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the

device will operate in 24-bit mode.

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below.

LRC are outputs. The frequencies of BCLK and LRC in master mode are controlled using MCLKDIV;

these clocks are divided down versions of PLL output clock (SYSCLK). The MCLKDIV default setting

provides a SYSCLK/256 division rate for the LRC output clock.

It is possible to divide down the BCLK rate using BCLKDIV; care must be taken in choosing the

correct BCLKDIV rate to maintain sufficient BCLK pulses per LRC period for the chosen data word

length. The BCLKDIV default setting provides a BCLK = SYSCLK clock.

WM8983GEFL/V Datasheet(PDF) 84 Page - Wolfson Microelectronics plc

WM8983GEFL/V Datasheet(HTML) 84 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL