OR4E2 datasheet(25/124 Pages) AGERE

25 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells (continued)

5-5748(F)

Figure 19. Decoder Mode

PLC Latches/Flip-Flops

The eight general-purpose latches/FFs in the PFU can

be used in a variety of configurations. In some cases,

the configuration options apply to all eight latches/FFs

in the PFU and some apply to the latches/FFs on a nib-

blewide basis where the ninth FF is considered inde-

pendently. For other options, each latch/FF is

independently programmable. In addition, the ninth FF

can be used for a variety of functions.

Table 7 summarizes these latch/FF options. The

latches/FFs can be configured as either positive- or

negative-level sensitive latches, or positive or negative

edge-triggered FFs (the ninth register can only be a

FF). All latches/FFs in a given nibble of a PFU share

the same clock, and the clock to these latches/FFs can

be inverted. The input into each latch/FF is from either

the corresponding LUT output (F[7:0]) or the direct data

input (DIN[7:0]). The latch/FF input can also be tied to

logic 1 or to logic 0, which is the default.

Table 7. Configuration RAM Controlled Latch/

Flip-Flop Operation

* Not available for FF[8].

Each PFU has two independent programmable clocks,

clock enable CE[1:0], local set/reset LSR[1:0], and

front-end data selects SEL[1:0]. When CE is disabled,

each latch/FF retains its previous value when clocked.

The clock enable, LSR, and SEL inputs can be inverted

to be active-low.

DEC

SIN7

LOGIC 1 OR 0

SIN6

LOGIC 1 OR 0

SIN5

LOGIC 1 OR 0

SIN4

LOGIC 1 OR 0

SIN9

LOGIC 1 OR 0

SIN8

LOGIC 1 OR 0

SIN3

LOGIC 1 OR 0

SIN1

LOGIC 1 OR 0

SIN2

LOGIC 1 OR 0

SIN0

LOGIC 1 OR 0

Function

Options

Common to All Latches/FFs in PFU

Enable GSRN

GSRN enabled or has no effect on

PFU latches/FFs.

Set Individually in Each Latch/FF in PFU

Set/Reset Mode

Set or reset.

By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8])

Clock Enable

CE or none.

LSR Control

LSR or none.

Clock Polarity

Noninverted or inverted.

Latch/FF Mode

Latch or FF.

LSR Operation

Asynchronous or synchronous.

Front-end Select* Direct (DIN[7:0]) or from LUT

(F[7:0]).

LSR Priority

Either LSR or CE has priority.

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