OR4E2 datasheet(51/124 Pages) AGERE

51 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Embedded System Bus (ESB) (continued)

Table 29. Status Register Space Assignments

Table 30. Command Register Space Assignments

Byte

Bit

Read/Write

Description

7:0

—

Reserved

7:0

—

Reserved

Configuration write data acknowledge

Readback data ready

Unassigned (zero)

FPSC_BIT_ERR

2RO

RAM_BIT_ERR

Configuration write data size (1, 2, or 4 bytes)

Use with above for HSIZE[1:0] (byte, half-word, word)

Readback addresses out of range

Error response received by CFG from system bus

Error responses received by CFG from system bus

Unassigned (zero)

ERR_FLAG 1

ERR_FLAG 0

Byte

Bit

Description

Bus reset from MPI > drives HRESETn

Bus reset from USER > drives HRESETn

Bus reset from FPSC > drives HRESETn

SYS_DAISY

REPEAT_RDBK (Don't increment readback address.)

MPI_USR_ENABLE

Readback data size (1, 2, or 4 bytes)

Use with above for HSIZE[1:0]

R/W SYS_GSR (GSR Input)

SYS_RD_CFG (similar to FPGA pin RD_CFGN, but active-high)

PRGM from MPI > (similar to FPGA pin, but active-high)

PRGM from USER > (similar to FPGA pin, but active-high)

PRGM from FPSC > (similar to FPGA pin, but active-high)

2LOCK from MPI

1LOCK from USER

LOCK from FPSC

7:0

Reserved

7:0

Reserved

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