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OR4E2 Datasheet(PDF) 63 Page - Agere Systems

Part # OR4E2
Description  Field-Programmable Gate Arrays
PDF  124 Pages
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Manufacturer  AGERE [Agere Systems]
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OR4E2 Datasheet(HTML) 63 Page - Agere Systems

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Lucent Technologies Inc.
63
Preliminary Data Sheet
December 2000
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
Table 38. Configuration Modes
Master Parallel Mode
The master parallel configuration mode is generally used to interface to industry-standard, bytewide memory. Fig-
ure 38 provides the connections for master parallel mode. The FPGA outputs an 18-bit address on A[17:0] to mem-
ory and reads 1 byte of configuration data on the rising edge of RCLK. The parallel bytes are internally serialized
starting with the least significant bit, D0. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only
if a standard prom file format is used. If a .bit or .rbt file is used from ORCA Foundry, then the user must mirror the
bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the
microprocessor.
5-9738(F)
Figure 38. Master Parallel Configuration Schematic
M3
M2
M1
M0
CCLK
Configuration Mode
Data
0
0
0
0
Output. High-frequency. Master Serial
Serial
0
1
0
0
Output. High-frequency. Master Parallel
8-bit
0
1
0
1
Output. High-frequency. Asynchronous Peripheral
8-bit
0
1
1
1
NA.
Reserved
NA
1
0
0
0
Output. Low-frequency. Master Serial
Serial
1
0
0
1
Input.
Slave Parallel
8-bit
1
0
1
0
Output.
MPC860 MPI
8-bit
1
0
1
1
Output.
MPC860 MPI
16-bit
1
1
0
0
Output. Low-frequency. Master Parallel
8-bit
1
1
0
1
Output. Low-frequency. Asynchronous Peripheral
8-bit
1
1
1
0
Output.
MPC860 MPI
32-bit
1
1
1
1
Input.
Slave Serial
Serial
A[21:0]
D[7:0]
EPROM
OE
CE
PRGM
A[21:0]
D[7:0]
DONE
ORCA
SERIES
FPGA
DOUT
CCLK
HDC
LDC
RCLK
M2
M1
M0
PROGRAM
VDD
VDD OR GND
TO DAISY-
CHAINED
DEVICES



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