OR4E2 datasheet(6/124 Pages) AGERE

6 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Product Description

Architecture Overview

The ORCA Series 4 architecture is a new generation of

SRAM-based programmable devices from Lucent

Technologies Microelectronics Group. It includes

enhancements and innovations geared toward today’s

high-speed systems on a single chip. Designed with

networking applications in mind, the Series 4 family

incorporates system-level features that can further

reduce logic requirements and increase system speed.

ORCA Series 4 devices contain many new patented

enhancements and are offered in a variety of packages

and speed grades.

The hierarchical architecture of the logic, clocks, rout-

ing, RAM, and system-level blocks create a seamless

merge of FPGA and ASIC designs. Modular hardware

and software technologies enable system-on-chip inte-

gration with true plug-and-play design implementation.

The architecture consists of four basic elements: pro-

grammable logic cells (PLCs), programmable input/out-

put cells (PIOs), embedded block RAMs (EBRs), and

system-level features. These elements are intercon-

nected with a rich routing fabric of both global and local

wires. An array of PLCs and its associated resources

are surrounded by common interface blocks (CIBs) that

provide an abundant interface to the adjacent PIOs or

system blocks. Routing congestion around these criti-

cal blocks is eliminated by the use of the same routing

fabric implemented within the programmable logic core.

PICs provide the logical interface to the PIOs which

provide the boundary interface off and onto the device.

Also, the interquad routing blocks (hIQ, vIQ) separate

the quadrants of the PLC array and provide the global

routing and clocking elements. Each PLC contains a

PFU, SLIC, local routing resources, and configuration

RAM. Most of the FPGA logic is performed in the PFU,

but decoders, PAL-like functions, and 3-state buffering

can be performed in the SLIC. The PIOs provide device

inputs and outputs and can be used to register signals

and to perform input demultiplexing, output multiplex-

ing, uplink and downlink functions, and other functions

on two output signals.

The Series 4 architecture integrates macrocell blocks

of memory known as EBR. The blocks run horizontally

across the PLC array and provide flexible memory

functionality. Large blocks of 512 x 18 quad-port RAM

complement the existing distributed PFU memory. The

RAM blocks can be used to implement RAM, ROM,

FIFO, multiplier, and CAM.

System-level functions such as a microprocessor inter-

face, PLLs, embedded system bus elements (located in

the corners of the array), the routing resources, and

configuration RAM are also integrated elements of the

architecture.

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