OR4E2 datasheet(77/124 Pages) AGERE

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Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Special-Purpose Pins (continued)

A[17:0]

During MPI mode, the A[17:0] are used as the address bus driven by the PowerPC bus

master utilizing the least significant bits of the PowerPC 32-bit address.

During master parallel configuration mode, A[17:0] address the configuration EPROM. In

MPI mode, many of the A[n] pins have alternate uses as described below. See the Special

Function Blocks section for more MPI information. During configuration, if not in master par-

allel or an MPI configuration mode, these pins are 3-stated with a pull-up enabled.

MPI_BURST

A[21] is used as the MPI_BURST. It is driven low to indicate a burst transfer is in progress.

Driven high indicates that the current transfer is not a burst.

MPI_BDIP

A[22] is used as the MPI_BDIP. It is driven by the PowerPC processor. Assertion of this pin

indicates that the second beat in front of the current one is requested by the master.

Negated before the burst transfer ends to abort the burst data phase.

MPI_TSZ[1:0]

A[19:18] are used as the MPI_TSZ[1:0] signals and are driven by the bus master to indicate

the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word.

During master parallel mode A[21:0], address the configuration EPROMs up to 4M bytes.

A[21:0]

If not used for MPI, these pins are user-programmable I/O pins.*

MPI_ACK

OIn PowerPC mode MPI operation, this is driven low indicating the MPI received the data on

the write cycle or returned data on a read cycle.

MPI_CLK

This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can

be a source of the clock for the embedded system bus. If MPI is used, this can be the AMBA

bus clock.

MPI_TEA

A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on

the internal system bus for the current transaction.

MPI_RTRY

This pin requests the MPC860 to relinquish the bus and retry the cycle.

D[31:0]

I/O Selectable data bus width from 8, 16, 32 bits. Driven by the bus master in a write transac-

tion. Driven by MPI in a read transaction.

D[7:0] receive configuration data during master parallel, peripheral, and slave parallel con-

figuration modes and each pin has a pull-up enabled. During serial configuration modes, D0

is the DIN input.

D[7:3] output internal status for asynchronous peripheral mode when RD is low.

After configuration, the pins are user-programmable I/O pins.*

DP[3:0]

I/O Selectable parity bus width from 1, 2, 4-bit, DP[0] for D[7:0], DP[1] for D[15:8], DP[2] for

D[23:16], and DP[3] for D[32:24].

After configuration, this pin is a user-programmable I/O pin.*

DIN

During slave serial or master serial configuration modes, DIN accepts serial configuration

data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input.

During configuration, a pull-up is enabled.

I/O After configuration, this pin is a user-programmable I/O pin.*

DOUT

During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained

slave devices. Data out on DOUT changes on the rising edge of CCLK.

I/O After configuration, DOUT is a user-programmable I/O pin.*

Symbol

I/O

Description

* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE

release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the acti-

vation of all user I/Os) is controlled by a second set of options.

Pin Information (continued)

Table 42. Pin Descriptions (continued)

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