OR4E2 datasheet(55/124 Pages) AGERE

55 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Phase-Locked Loops (continued)

Table 35. Phase-Lock Loops Index

FPGA States of Operation

Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration,

and start-up. Figure 33 outlines these three states.

5-4529(F).

Figure 33. FPGA States of Operation

Name

Description

[UL][LL][UR][LR]PPLL

Universal user-programmable PLL (20 MHz—200 MHz)

[UL][LL]HPPLL

Universal user-programmable PLL (60 MHz—420 MHz)

URPLL1

DS-1/E-1 dedicated PLL

LRPLL2

STS-1/STM-1 dedicated PLL

– ACTIVE I/O

– RELEASE INTERNAL RESET

– DONE GOES HIGH

START-UP

INITIALIZATION

CONFIGURATION

RESET

PRGM

LOW

PRGM

LOW

– CLEAR CONFIGURATION MEMORY

– INIT LOW, HDC HIGH, LDC LOW

OPERATION

POWERUP

– POWER-ON TIME DELAY

– M[3:0] MODE IS SELECTED

– CONFIGURATION DATA FRAME WRITTEN

– INIT HIGH, HDC HIGH, LDC LOW

– DOUT ACTIVE

YES

RESET,

INIT,

PRGM

LOW

BIT

ERROR

YES

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