OR4E2 datasheet(53/124 Pages) AGERE

53 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Phase-Locked Loops (continued)

Table 32. DPLL DS-1/E-1 Specifications

A dedicated pin PLL_VF is needed for externally connecting a low-pass filter circuit, as shown in Table 33. This pro-

vides the specified DS–1/E–1 PLL operating condition.

1001(F).

Figure 31. PLL_VF External Requirements

Parameter

Min

Nom

Max

Unit

VDD1.5

1.425

1.5

1.575

VDD3.3

3.0

3.3

3.6

Operating Temp

–40

125

°C

Input Clock Voltage

1.425

1.5

1.575

Output Clock Voltage

1.425

1.5

1.575

Input Clock Frequency

1.0

—

2.5

MHz

Output Clock Frequency

—

1.544

—

MHz

—

2.048

—

Input Duty Cycle Tolerance

—

Output Duty Cycle

dc Power

—

Total On Current

—

2.5

—

Total Off Current

—

Cycle to Cycle Jitter (p-p)

0.015 at 1.544 MHz

UIp-p

0.05 at 2.048 MHz

Lock Time

—

<1200

—

µs

PLL1

LPPLL

PLL2

LPPLL

HPPLL

LPPLL

PLL_VF

DEDICATED

VSS

RC2

R = 6 k

Ω WITH 1% ACCURACY

C1 = 100 pF 5% ACCURACY

C2 = 0.01

µF 5% ACCURACY

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