MSP430F6776IPZ datasheet(31/157 Pages) TI

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ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

www.ti.com

SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013

Flash Memory (Link to User's Guide)

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

•

Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also

called information memory.

•

Segment A can be locked separately.

RAM Memory (Link to User's Guide)

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage;

however, all data is lost. Features of the RAM memory include:

•

RAM memory has n sectors of 4K bytes each.

•

Each sector 0 to n can be complete disabled, however data retention is lost.

•

Each sector 0 to n automatically enters low power retention mode when possible.

Backup RAM Memory (Link to User's Guide)

The Backup RAM provides a limited number of bytes of RAM that are retained during LPM3.5. This Backup RAM

is part of the Backup subsystem that operates on dedicated power supply AUXVCC3.There are 8 bytes of

Backup RAM available in this device. It can be wordwise accessed via the registers BAKMEM0, BAKMEM1,

BAKMEM2, and BAKMEM3. The Backup RAM registers cannot be accessed by CPU when the high-side SVS is

disabled by the user application.

Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide

(SLAU208).

Oscillator and System Clock (Link to User's Guide)

The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal

very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), and an

integrated internal digitally controlled oscillator (DCO). The UCS module is designed to meet the requirements of

both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL)

hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple

of the selected FLL reference frequency. The internal DCO provides a fast turn-on clock source and stabilizes in

less than 5 µs. The UCS module provides the following clock signals:

•

Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator (VLO), or

the trimmed low-frequency oscillator (REFO).

•

Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made

available to ACLK.

•

Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources made available to ACLK.

•

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

Power Management Module (PMM) (Link to User's Guide)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor

(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power-on and power-off. The

SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply

voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not

automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

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