MSP430F6776IPZ datasheet(36/157 Pages) TI

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ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013

www.ti.com

Table 19. DMA Trigger Assignments(1) (continued)

CHANNEL

TRIGGER

UCA1RXIFG

UCA1TXIFG

UCA2RXIFG

UCA2TXIFG

UCB0RXIFG0

UCB0TXIFG0

ADC10IFG0

UCA3RXIFG

UCA3TXIFG

UCB1RXIFG0

UCB1TXIFG0

MPY ready

DMA2IFG

DMA0IFG

DMA1IFG

Reserved

CRC16 (Link to User's Guide)

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data

checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

Hardware Multiplier (Link to User's Guide)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with

32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication

as well as signed and unsigned multiply and accumulate operations.

AES128 Accelerator (Link to User's Guide)

The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys according to

the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.

Enhanced Universal Serial Communication Interface (eUSCI) (Links to User's Guide: UART Mode,

SPI Mode, I2C Mode)

The eUSCI module is used for serial data communication. The eUSCI module supports synchronous

communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as

UART, enhanced UART with automatic baudrate detection, and IrDA.

The eUSCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.

The eUSCI_Bn module provides support for SPI (3 or 4 pin) and I2C.

Four eUSCI_A and two eUSCI_B module are implemented in MSP430F677x devices.

ADC10_A (Link to User's Guide)

The ADC10_A module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator and a conversion results buffer. A window comparator with a

lower and upper limit allows CPU independent result monitoring with three window comparator interrupt flags.

SD24_B (Link to User's Guide)

The SD24_B module integrates up to seven independent 24-bit sigma-delta A/D converters. Each converter is

designed with a fully differential analog input pair and programmable gain amplifier input stage. Also the

converters are based on second-order over-sampling sigma-delta modulators and digital decimation filters. The

decimation filters are comb type filters with selectable oversampling ratios of up to 1024.

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