AT24C01D and AT24C02D [DATASHEET]

Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014

7

4.

Memory Organization

The AT24C01D is internally organized as 16 pages of 8 bytes each while the AT24C02D is organized as 32 pages

of 8 bytes each.

4.1

Device Addressing

Accessing the device requires an 8-bit Device Address word following a Start condition to enable the device for a

Read or Write operation. Since multiple slave devices can reside on the serial bus, each slave device must have its

own unique address so that the Master can access each device independently.

The most significant four bits of the Device Address word is referred to as the device type identifier. The device

type identifier ‘

These hardwired address pins use an internal proprietary circuit that automatically biases each pin to a Logic 0

state if the pin is allowed to float. In order to operate in a wide variety of application environments, the pull-down

mechanism is intentionally designed to be somewhat strong. Once the pin is biased above the CMOS input buffer’s

pins to a known state whenever possible.

mentioned automatic pull-down circuit will set these signals to a Logic 0 state. As a result, to properly communicate

operation. This requirement has been shown in Table 4-1.

The eighth bit of the Device Address (bit 0) is the Read/Write operation select bit. A Read operation is initiated if

this bit is high and a Write operation is initiated if this bit is low.

Upon the successful comparison of the Device Address, the EEPROM will return an ACK. If a valid comparison is

not made, the device will NACK and return to a standby state.

Table 4-1.

Device Address Byte

For all operations except the Current Address Read, a Word Address byte must be transmitted to the device

immediately following the Device Address byte. The Word Address byte contains a 7-bit (in the case of the

AT24C01D) or 8-bit (in the case of the AT24C02D) memory array address, and is used to specify which location in

the EEPROM to start reading or writing. Please refer to Table 4-2 to review these bit positions.

Table 4-2.

Word Address Byte

Note:

1.

The A7 bit is a don’t care bit for the AT24C01D.

The relationship of the AC timing parameters with respect to SCL and SDA for the AT24C01D/02D are shown in

the timing waveform in Figure 8-1 on page 14. The AC timing characteristics and specifications are outlined in

Section 8.4 “AC Characteristics” on page 14.

Package

Device Type Identifier

Hardware Slave Address Bits

Read/ Write

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SOIC, TSSOP, UDFN,

PDIP, VFBGA

1

0

1

0

R/W

SOT23

1

0

1

0

0

0

0

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

A7(1)

A6

A5

A4

A3

A2

A1

A0