AT24C01D and AT24C02D [DATASHEET]

Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014

9

Figure 5-2.

Page Write

5.3

Acknowledge Polling

An Acknowledge Polling routine can be implemented to optimize time sensitive applications that would prefer not to

Serial EEPROM write cycle has completed, so a subsequent operation can be started.

Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated. This

involves repeatedly sending a Start condition followed by a valid Device Address byte with the R/W bit set at

Logic 0. The device will not respond with an ACK while the write cycle is ongoing. Once the internal write cycle has

completed, the EEPROM will respond with an ACK, allowing a new Read or Write operation to be immediately

initiated. A flow chart has been included below in Figure 5-3 to better illustrate this technique.

Figure 5-3.

Acknowledge Polling Flow Chart

SCL

SDA

Start

by

Master

ACK

from

Slave

ACK

from

Slave

Device Address Byte

Word Address Byte

MSB

MSB

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

0

A

2

A

1

A

0

0

0

ACK

from

Slave

Stop

by

Master

ACK

from

Slave

Data Word (n)

Data Word (n+x), max of 8 without rollover

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

MSB

MSB

A7

A6

A5

A4

A3

A2

A1

A0

0

D7

D6

D5

D4

D3

D2

D1

D0

0

D7

D6

D5

D4

D3

D2

D1

D0

0

Did

the device

ACK?

Send any

Write

protocol

Send

Stop

condition

to initiate the

write cycle

Send Start

condition followed

by a valid

Device Address

byte with R/W = 0

Proceed to

next Read or

Write operation

NO

YES