 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AT24C01D Datasheet(PDF) 2 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AT24C01D Datasheet(HTML) 2 Page - ATMEL Corporation |
|
|
2 / 26 page  AT24C01D and AT24C02D [DATASHEET] Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014 2 1. Pin Descriptions and Pinouts Table 1-1. Pin Descriptions Note: 1. If the A0, A1, A2, or WP pins are not driven, they are internally pulled down to GND. In order to operate in a wide variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong. Once these pins are biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull-down mechanism disengages. Atmel recommends connecting these pins to a known state whenever possible. Note: 1. Refer to “Device Addressing” on page 7 for details about addressing the SOT23 version of the device. Pin Number Pin Symbol Pin Name and Functional Description Asserted State Pin Type 1, 2, 3 A0, A1, A2 Device Address Inputs: The A0, A1, and A2 pins are used to select the hardware device address and correspond to the seventh, sixth, and fifth bit of the I2C seven bit slave address. These pins can be directly connected to VCC or GND, allowing up to eight devices on the same bus. Refer to Note 1 for behavior of the pin when not connected. — Input 4 GND Ground: The ground reference for the power supply. GND should be connected to the system ground. — Power 5 SDA Serial Data: The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. The SDA pin must be pulled-high using an external pull-up resistor (not to exceed 10K in value) and may be wire-ORed with any number of other open-drain or open-collector pins from other devices on the same bus. — Input/ Output 6 SCL Serial Clock: The SCL pin is used to provide a clock to the device and to control the flow of data to and from the device. Command and input data present on the SDA pin is always latched in on the rising edge of SCL, while output data on the SDA pin is clocked out on the falling edge of SCL. The SCL pin must either be forced high when the serial bus is idle or pulled-high using an external pull-up resistor. — Input 7 WP Write Protect: Connecting the WP pin to GND will ensure normal write operations.When the WP pin is connected to VCC, all write operations to the memory are inhibited. Refer to Note 1 for behavior of the pin when not connected. High Input 8 VCC Device Power Supply: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. — Power A0 A1 A2 GND VCC WP SCL SDA 8-lead SOIC Top View Note: Package drawings are not to scale 8 7 6 5 8-lead TSSOP Top View 1 2 3 4 8 7 6 5 A0 A1 A2 GND VCC WP SCL SDA Top View 8 7 6 5 1 2 3 4 8-pad UDFN A0 A1 A2 GND VCC WP SCL SDA VCC WP SCL SDA A0 A1 A2 GND 1 2 3 4 8 7 6 5 8-ball VFBGA Top View Top View SCL GND SDA WP VCC 5-lead SOT23 (1) 1 2 3 5 4 1 2 3 4 Top View 8-lead PDIP A0 A1 A2 GND VCC WP SCL SDA 8 7 6 5 1 2 3 4 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
