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AT24C01D Datasheet(PDF) 10 Page - ATMEL Corporation

Part # AT24C01D
Description  IC-Compatible (2-wire) Serial EEPROM
PDF  26 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT24C01D Datasheet(HTML) 10 Page - ATMEL Corporation

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AT24C01D and AT24C02D [DATASHEET]
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014
10
5.4
Write Cycle Timing
The length of the self-timed write cycle, or tWR, is defined as the amount of time from the Stop condition that begins
the internal Write operation, to the Start condition of the first Device Address byte sent to the AT24C01D/02D
which it subsequently responds to with an ACK. Figure 5-4 has been included to show this measurement. During
the internally self-timed write cycle, any attempts to read or write to the memory array will not be processed.
Figure 5-4.
Write Cycle Timing
5.5
Write Protection
The AT24C01D/02D utilizes a hardware data protection scheme that allows the user to write protect the entire
memory contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pin is at GND
or left floating.
Table 5-1.
AT24C01D/02D Write Protect Behavior
The status of the WP pin is sampled at the Stop condition for every Byte Write or Page Write command prior to the
start of an internally self-timed Write operation. Changing the WP pin state after the Stop condition has been sent
will not alter or interrupt the execution of the write cycle. The WP pin state must be valid with respect to the
associated setup (tSU.WP) and hold (tHD.WP) as shown in the Figure 5-5 below. The WP setup time is the amount of
time that the WP state must be stable before the Stop condition is issued. The WP hold time is the amount of time
after the Stop condition that the WP state must remain stable.
If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the
Device Address, Word address, and Data bytes but no write cycle will occur when the Stop condition is issued, and
the device will immediately be ready to accept a new Read or Write command.
Figure 5-5.
Write Protect Setup and Hold Timing
t
WR
Stop
Condition
Start
Condition
Data Word n
ACK
D0
SDA
Stop
Condition
SCL
89
ACK
First Acknowledge from the device
to a valid device address sequence after
write cycle is initiated. The minumum t
WR
can only be determined through
the use of an ACK Polling routine.
9
WP Pin Voltage
Part of the Array Protected
VCC
Full Array
GND
None — Write Protection Not Enabled
SCL
SDA IN
1
2
7
8
9
D7
D6
D1
D0
WP
tSU.WP
Stop
by
Master
Data Word Input Sequence Page/Byte Write Operation
ACK by Slave
tHD.WP



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