AT24C01D and AT24C02D [DATASHEET]

Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014

11

6.

Read Operations

Read operations are initiated the same way as Write operations with the exception the read/write select bit in the

Device Address word must be a Logic 1. There are three Read operations:



Current Address Read



Random Address Read



Sequential Read

6.1

Current Address Read

The internal data word address counter maintains the last address accessed during the last Read or Write

the part. The address roll-over during read is from the last byte of the last page to the first byte of the first page of

the memory.

A Current Address Read operation will output data according to the location of the internal data word address

counter. This is initiated with a Start condition, followed by a valid Device Address byte with the R/W bit set to

Logic 1. The device will ACK this sequence and the current address data word is serially clocked out on the SDA

line. All types of Read operations will be terminated if the bus Master does not respond with an ACK (it NACKs)

during the ninth clock cycle. A Read instruction may be terminated at any point with a Stop condition which will

force the device into standby mode.

Figure 6-1.

Current Address Read

6.2

Random Read

A Random Read begins in the same way as a Byte Write operation does to load in a new data word address. This

is known as a “dummy write” sequence. However, the Data Byte and the Stop condition of the Byte Write must be

omitted to prevent the part from entering an internal write cycle. Once the Device Address and Word Address are

clocked in and acknowledged by the EEPROM, the bus Master must generate another Start condition. The bus

Master now initiates a Current Address Read by sending a Start condition, followed by a valid Device Address byte

with the R/W bit set to Logic 1. The EEPROM will ACK the Device Address and serially clock out the data word on

the SDA line. All types of Read operations will be terminated if the bus Master does not respond with an ACK (it

NACKs) during the ninth clock cycle. A Read instruction may be terminated at any point with a Stop condition

which will force the device into standby mode.

SCL

SDA

Device Address Byte

Data Word (n)

Start

by

Master

ACK

from

Slave

NACK

from

Master

Stop

by

Master

MSB

MSB

1

0

1

0

A

2

A

1

A

0

1

0

D7

D6

D5

D4

D3

D2

D1

D0

1

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9