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AN3077 Datasheet(PDF) 6 Page - STMicroelectronics |
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AN3077 Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 82 page ![]() List of figures AN3077 6/82 DocID16384 Rev 10 List of figures Figure 1. Double Read Digital Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 2. Double Read PWM Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 3. Double encoder read input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 4. Write Digital Output With Read Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 5. Double Write Digital Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 6. Double Write PWM Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 7. Single Write PWM Output With Read Back configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. Single Read Analog Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 9. Software BISTs to test the multiplexing circuitry (ADC_SWTEST_TEST1) . . . . . . . . . . . . 40 Figure 10. Implementation of ADC_SW_TEST1 through the ADC presample feature . . . . . . . . . . . . 41 Figure 11. Software BISTs to test the multiplexing circuitry (ADC_SWTEST_TEST2) . . . . . . . . . . . . 41 Figure 12. Implementation of ADC_SW_TEST2 through the ADC presample feature . . . . . . . . . . . . 41 Figure 13. Series of acquired analog values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 14. Double Read Analog Inputs configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 15. Logic scheme of the LVD_DIG and HVD_DIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 16. Logic scheme of the LVD_FLASH, LVD_GPIO and LVD_VREG . . . . . . . . . . . . . . . . . . . . 52 Figure 17. Example of QFP144 pin/pad adjacency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 18. BGA balls non-adjacent, die pads adjacent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 19. BGA balls adjacent, die pads non-adjacent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 |
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