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PIC18LC658T-E/CL Datasheet(PDF) 24 Page - Microchip Technology |
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PIC18LC658T-E/CL Datasheet(HTML) 24 Page - Microchip Technology |
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24 / 366 page  PIC18CXX8 DS30475A-page 24 Advanced Information 2000 Microchip Technology Inc. 2.5 HS4 (PLL) A Phase Locked Loop circuit is provided as a pro- grammable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4. For an input clock frequency of 10 MHz, the internal clock frequency will be multiplied to 40 MHz. This is useful for customers who are concerned with EMI due to high frequency crystals. The PLL can only be enabled when the oscillator con- figuration bits are programmed for HS mode. If they are programmed for any other mode, the PLL is not enabled and the system clock will come directly from OSC1. The PLL is one of the modes of the FOSC2:FOSC0 configuration bits. The oscillator mode is specified dur- ing device programming. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out referred to as TPLL. FIGURE 2-5: PLL BLOCK DIAGRAM VCO Loop Filter Divide by 4 Crystal Osc OSC2 OSC1 FIN FOUT SYSCLK Phase Comparator FOSC2:FOSC0 = ‘110’ |
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