PIC18LC658T-ESLASHCL datasheet(70/366 Pages) MICROCHIP

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PIC18CXX8

DS30475A-page 70

Advanced Information

 2000 Microchip Technology Inc.

5.2.3

LONG WRITE INTERRUPTS

The long write must be terminated by a RESET or any

interrupt.

The interrupt source must have its interrupt enable bit

set. When the source sets its interrupt flag, program-

ming will terminate. This will occur regardless of the

settings of interrupt priority bits, the GIE/GIEH bit or the

PIE/GIEL bit.

Depending on the states of interrupt priority bits, the

GIE/GIEH bit or the PIE/GIEL bit, program execution

can either be vectored to the high or low priority Inter-

rupt Service Routine (ISR), or continue execution from

where programming commenced.

In either case, the interrupt flag will not be cleared

when programming is terminated and will need to be

cleared by the software.

5.3

Unexpected Termination of Write

Operations

If a write is terminated by an unplanned event such as

loss of power, an unexpected RESET, or an interrupt

that was not disabled, the memory location just pro-

grammed should be verified and reprogrammed if

needed.

TABLE 5-2:

SLEEP MODE, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS

GIE/

GIEH

PIE/

GIEL

Priority

Interrupt

Enable

Interrupt

Flag

Action

(default)

Long write continues even if interrupt flag

becomes set during SLEEP.

Long write continues, will wake when

the interrupt flag is set.

(default)

Terminates long write, executes next instruction.

Interrupt flag not cleared.

(default)

high priority

(default)

Terminates long write, executes next instruction.

Interrupt flag not cleared.

(default)

low

Terminates long write, executes next instruction.

Interrupt flag not cleared.

(default)

low

Terminates long write, branches to low priority

interrupt vector.

Interrupt flag can be cleared by ISR.

(default)

high priority

(default)

Terminates long write, branches to high priority

interrupt vector.

Interrupt flag can be cleared by ISR.

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