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PIC18LC658T-E/CL Datasheet(PDF) 34 Page - Microchip Technology |
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PIC18LC658T-E/CL Datasheet(HTML) 34 Page - Microchip Technology |
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34 / 366 page  PIC18CXX8 DS30475A-page 34 Advanced Information 2000 Microchip Technology Inc. TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU 658 858 ---0 0000 ---0 0000 ---0 uuuu (3) TOSH 658 858 0000 0000 0000 0000 uuuu uuuu (3) TOSL 658 858 0000 0000 0000 0000 uuuu uuuu (3) STKPTR 658 858 00-0 0000 00-0 0000 uu-u uuuu (3) PCLATU 658 858 ---0 0000 ---0 0000 ---u uuuu PCLATH 658 858 0000 0000 0000 0000 uuuu uuuu PCL 658 858 0000 0000 0000 0000 PC + 2 (2) TBLPTRU 658 858 --00 0000 --00 0000 --uu uuuu TBLPTRH 658 858 0000 0000 0000 0000 uuuu uuuu TBLPTRL 658 858 0000 0000 0000 0000 uuuu uuuu TABLAT 658 858 0000 0000 0000 0000 uuuu uuuu PRODH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 658 858 0000 000x 0000 000u uuuu uuuu (1) INTCON2 658 858 1111 1111 1111 1111 uuuu uuuu (1) INTCON3 658 858 1100 0000 1100 0000 uuuu uuuu (1) INDF0 658 858 N/A N/A N/A POSTINC0 658 858 N/A N/A N/A POSTDEC0 658 858 N/A N/A N/A PREINC0 658 858 N/A N/A N/A PLUSW0 658 858 N/A N/A N/A FSR0H 658 858 ---- 0000 ---- 0000 ---- uuuu FSR0L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu WREG 658 858 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 658 858 N/A N/A N/A POSTINC1 658 858 N/A N/A N/A POSTDEC1 658 858 N/A N/A N/A PREINC1 658 858 N/A N/A N/A PLUSW1 658 858 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. |
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