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PIC18LC658T-E/CL Datasheet(PDF) 53 Page - Microchip Technology |
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PIC18LC658T-E/CL Datasheet(HTML) 53 Page - Microchip Technology |
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53 / 366 page  2000 Microchip Technology Inc. Advanced Information DS30475A-page 53 PIC18CXX8 INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) n/a n/a POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) n/a n/a POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) n/a n/a PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) n/a n/a PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by WREG n/a n/a FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- 0000 ---- 0000 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx uuuu uuuu STATUS — — — NOV Z DC C ---x xxxx ---u uuuu TMR0H Timer0 register high byte 0000 0000 0000 0000 TMR0L Timer0 register low byte xxxx xxxx uuuu uuuu T0CON TMR0ON T08BIT T0CS T0SE T0PS3 T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 OSCCON — — — — — — — SCS ---- ---0 ---- ---0 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 --00 0101 WDTCON — — — — — — — SWDTEN ---- ---0 ---- ---0 RCON IPEN LWRT — RI TO PD POR BOR 00-1 11qq 00-q qquu TMR1H Timer1 Register High Byte xxxx xxxx uuuu uuuu TMR1L Timer1 Register Low Byte xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu TMR2 Timer2 Register 0000 0000 0000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 0000 0000 SSPSTAT SMP CKE D/A PS R/W UA BF 0000 0000 0000 0000 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000 ADCON2 ADFM — — — — ADCS2 ADCS1 ADCS0 0--- -000 0--- -000 Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS(3) Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. |
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