PIC18LC658T-ESLASHCL datasheet(88/366 Pages) MICROCHIP

88 / 366 page

PIC18CXX8

DS30475A-page 88

Advanced Information

 2000 Microchip Technology Inc.

7.1.6

INT INTERRUPTS

External interrupts on the RB0/INT0, RB1/INT1,

RB2/INT2, and RB3/INT3 pins are edge triggered:

either rising if the corresponding INTEDGx bit is set in

the INTCON2 register, or falling, if the INTEDGx bit is

clear. When a valid edge appears on the RBx/INTx pin,

the corresponding flag bit INTxIF is set. This interrupt

can be disabled by clearing the corresponding enable

bit INTxIE. Flag bit INTxIF must be cleared in software

in the Interrupt Service Routine before re-enabling the

interrupt. All external interrupts (INT0, INT1, INT2, and

INT3) can wake-up the processor from SLEEP, if bit

INTxIE was set prior to going into SLEEP. If the global

interrupt enable bit GIE is set, the processor will branch

to the interrupt vector following wake-up.

Interrupt priority for INT1, INT2 and INT3 is determined

by the value contained in the interrupt priority bits

INT1IP (INTCON3 register), INT3IP (INTCON3 regis-

ter), and INT2IP (INTCON2 register). There is no prior-

ity bit associated with INT0; it is always a high priority

interrupt source.

7.1.7

TMR0 INTERRUPT

In 8-bit mode (which is the default), an overflow (FFh

→

00h) in the TMR0 register will set flag bit TMR0IF. In

16-bit mode, an overflow (FFFFh

→ 0000h) in the

TMR0H:TMR0L registers will set flag bit TMR0IF. The

interrupt can be enabled/disabled by setting/clearing

enable bit TMR0IE (INTCON register). Interrupt priority

for Timer0 is determined by the value contained in the

interrupt priority bit TMR0IP (INTCON2 register). See

Section 10.0 for further details on the Timer0 module.

7.1.8

PORTB INTERRUPT-ON-CHANGE

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON register). The interrupt can be enabled/

disabled by setting/clearing enable bit RBIE (INTCON

Interrupt

priority

for

PORTB

interrupt-

on-change is determined by the value contained in the

interrupt priority bit RBIP (INTCON2 register).

7.2

Context Saving During Interrupts

During an interrupt, the return PC value is saved on the

stack. Additionally, the WREG, STATUS and BSR reg-

isters are saved on the fast return stack. If a fast return

from interrupt is not used (See Section 4.3), the user

may need to save the WREG, STATUS and BSR regis-

ters in software. Depending on the user’s application,

other

registers

may

also

need

saved.

Example 7-1 saves and restores the WREG, STATUS

and BSR registers during an Interrupt Service Routine.

EXAMPLE 7-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

W_TEMP

; W_TEMP is in Low Access bank

MOVFF

STATUS, STATUS_TEMP

; STATUS_TEMP located anywhere

MOVFF

BSR, BSR_TEMP

; BSR located anywhere

;

; USER ISR CODE

;

MOVFF

BSR_TEMP, BSR

; Restore BSR

MOVF

W_TEMP, W

; Restore WREG

MOVFF

STATUS_TEMP, STATUS

; Restore STATUS

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