PIC18LC658T-ESLASHCL datasheet(30/366 Pages) MICROCHIP

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PIC18CXX8

DS30475A-page 30

Advanced Information

 2000 Microchip Technology Inc.

3.1

Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when a

VDD rise is detected. To take advantage of the POR cir-

cuitry, connect the MCLR pin directly (or through a

resistor) to VDD. This will eliminate external RC compo-

nents usually needed to create a Power-on Reset

delay. A minimum rise rate for VDD is specified (param-

eter D004). For a slow rise time, see Figure 3-2.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature,...) must be met to ensure

operation. If these conditions are not met, the device

must be held in RESET until the operating conditions

are met. Brown-out Reset may be used to meet the

voltage start-up condition.

FIGURE 3-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

3.2

Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(parameter #33), only on power-up from the POR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in RESET as long as the PWRT is

active. The PWRT’s time delay allows VDD to rise to an

acceptable level. A configuration bit (PWRTEN in

CONFIG2L register) is provided to enable/disable the

PWRT.

The power-up time delay will vary from chip to chip due

to VDD, temperature and process variation. See DC

parameter #33 for details.

3.3

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over (parameter #32). This ensures that

the crystal oscillator or resonator has started and stabi-

lized.

The OST time-out is invoked only for XT, LP, HS and

HS4 modes and only on Power-on Reset or wake-up

from SLEEP.

3.4

PLL Lock Time-out

With the PLL enabled, the time-out sequence following

a Power-on Reset is different from other oscillator

modes. A portion of the Power-up Timer is used to pro-

vide a fixed time-out that is sufficient for the PLL to lock

to the main oscillator frequency. This PLL lock time-out

(TPLL) is typically 2 ms and follows the oscillator

start-up time-out (OST).

3.5

Brown-out Reset (BOR)

configuration

bit,

BOREN,

can

disable

(if

clear/programmed) or enable (if set) the Brown-out

Reset circuitry. If VDD falls below parameter D005 for

greater than parameter #35, the brown-out situation

resets the chip. A RESET may not occur if VDD falls

below parameter D005 for less than parameter #35.

The chip will remain in Brown-out Reset until VDD rises

above BVDD. The Power-up Timer will then be invoked

and will keep the chip in RESET an additional time

delay (parameter #33). If VDD drops below BVDD while

the Power-up Timer is running, the chip will go back

into a Brown-out Reset and the Power-up Timer will be

initialized. Once VDD rises above BVDD, the Power-up

Timer will execute the additional time delay.

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 k

Ω is recommended to make sure

that the voltage drop across R does not

violate the device’s electrical specification.

3: R1 = 100

Ω to 1 kΩ will limit any current

flowing into MCLR from external capacitor

C in the event of MCLR/VPP pin break-

down due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

VDD

MCLR

PIC18CXX8

PIC18LC658T-E/CL Datasheet(PDF) 30 Page - Microchip Technology

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