PIC18LC658T-ESLASHCL datasheet(80/366 Pages) MICROCHIP

80 / 366 page

PIC18CXX8

DS30475A-page 80

Advanced Information

 2000 Microchip Technology Inc.

7.1.2

PIR REGISTERS

The Peripheral Interrupt Request (PIR) registers con-

tain the individual flag bits for the peripheral interrupts

(Register 7-5). Due to the number of peripheral inter-

rupt sources, there are three Peripheral Interrupt

Request (Flag) registers (PIR1, PIR2, PIR3).

7.1.3

PIE REGISTERS

The Peripheral Interrupt Enable (PIE) registers contain

the individual enable bits for the peripheral interrupts

(Register 7-5). Due to the number of peripheral inter-

rupt sources, there are three Peripheral Interrupt

Enable registers (PIE1, PIE2, PIE3). When IPEN is

clear, the PEIE bit must be set to enable any of these

peripheral interrupts.

7.1.4

IPR REGISTERS

The Interrupt Priority (IPR) registers contain the individ-

ual

priority

bits

for

the

peripheral

interrupts

(Register 7-7). Due to the number of peripheral inter-

rupt sources, there are three Peripheral Interrupt Prior-

ity registers (IPR1, IPR2, IPR3). The operation of the

priority bits requires that the Interrupt Priority Enable bit

(IPEN) be set.

7.1.5

RCON REGISTER

The Reset Control (RCON) register contains the bit that

is used to enable prioritized interrupts (IPEN).

RCON REGISTER

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON register).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt, and after servicing

that interrupt.

R/W-0

U-0

R/W-1

R/W-0

IPEN

LWRT

—

POR

BOR

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

= Enable priority levels on interrupts

= Disable priority levels on interrupts (16CXXX compatibility mode)

bit 6

LWRT: Long Write Enable