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PIC18LC658T-E/CL Datasheet(PDF) 109 Page - Microchip Technology |
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PIC18LC658T-E/CL Datasheet(HTML) 109 Page - Microchip Technology |
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109 / 366 page ![]() 2000 Microchip Technology Inc. Advanced Information DS30475A-page 109 PIC18CXX8 9.0 PARALLEL SLAVE PORT The Parallel Slave Port is an 8-bit parallel interface for transferring data between the PIC18CXX8 device and an external device. PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE (PSPCON register) is set. In Slave mode, it is asyn- chronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR. It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low. The PORTE I/O pins become control inputs for the microprocessor port when bit PSPMODE (PSPCON Register) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). In this mode, the input buffers are TTL. FIGURE 9-1: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data Bus WR LATD RDx Pin Q D CK EN QD EN RD PORTD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read Chip Select Write RD CS WR TTL TTL TTL TTL or WR PORTD RD LATD Data Latch Note: I/O pins have diode protection to VDD and VSS. |
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