PIC18LC658T-ESLASHCL datasheet(116/366 Pages) MICROCHIP

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PIC18CXX8

DS30475A-page 116

Advanced Information

 2000 Microchip Technology Inc.

10.3

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h in 8-bit mode or FFFFh

to 0000h in 16-bit mode. This overflow sets the TMR0IF

bit. The interrupt can be masked by clearing the

TMR0IE bit. The TMR0IF bit must be cleared in soft-

ware by the Timer0 module interrupt service routine

before re-enabling this interrupt. The TMR0 interrupt

cannot awaken the processor from SLEEP, since the

timer is shut off during SLEEP.

10.4

16-Bit Mode Timer Reads and Writes

Timer0 can be set in 16-bit mode by clearing T0CON

T08BIT. Registers TMR0H and TMR0L are used to

access 16-bit timer value.

TMR0H is not the high byte of the timer/counter in

16-bit mode, but is actually a buffered version of the

high byte of Timer0 (refer to Figure 10-1). The high byte

of the Timer0 counter/timer is not directly readable nor

writable. TMR0H is updated with the contents of the

high byte of Timer0 during a read of TMR0L. This pro-

vides the ability to read all 16-bits of Timer0 without

having to verify that the read of the high and low byte

were valid due to a rollover between successive reads

of the high and low byte.

A write to the high byte of Timer0 must also take place

through the TMR0H buffer register. Timer0 high byte is

updated with the contents of buffered value of TMR0H,

when a write occurs to TMR0L. This allows all 16 bits

of Timer0 to be updated at once.

TABLE 10-1:

REGISTERS ASSOCIATED WITH TIMER0

Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator

modes, they are disabled and read as ‘0’.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

TMR0L

Timer0 Module’s Low Byte Register

xxxx xxxx

uuuu uuuu

TMR0H

Timer0 Module’s High Byte Register

0000 0000

INTCON

GIE/GIEH

PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF

0000 000x

0000 000u

T0CON

TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2

T0PS1

T0PS0

1111 1111

TRISA

—

PORTA Data Direction Register(1)

--11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

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