PEB2256HT datasheet(33/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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FALC56 V1.2

PEB 2256

Pin Descriptions

Data Sheet

2002-08-27

RL2

I (analog)

Line Receiver 2

Analog input from the external transformer.

Selected if LIM1.DRS is cleared.

RDIN

Receive Data Input Negative

Input for received dual-rail PCM(-) route signal

which is latched with the internally recovered

receive route clock. An internal DPLL extracts

the receive route clock from the incoming data

pulses. The duty cycle of the received signal

has to be close to 50%.

The dual-rail mode is selected if LIM1.DRS

and FMR0.RC1 are set. Input polarity is

selected by bit RC0.RDIS (after reset: active

low), line coding is selected by FMR0.RC(1:0).

RCLKI

Receive Clock Input

Receive clock input for the optical interface if

LIM1.DRS is set and FMR0.RC(1:0) = 00.

Clock frequency: 2.048 MHz (E1) or

1.544 MHz (T1/J1).

RCLKI is ignored if CMI coding is selected.

Table 2

Pin Definitions - Line Interface (cont’d)

No.

Ball

No.

Symbol

Input (I)

Output (O)

Supply (S)

Function

PEB2256HT Datasheet(PDF) 33 Page - Infineon Technologies AG