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PEB2256HT Datasheet(PDF) 45 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 45 Page - Infineon Technologies AG |
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45 / 490 page ![]() FALC56 V1.2 PEB 2256 Pin Descriptions Data Sheet 45 2002-08-27 60 61 62 63 B8 A9 A8 B7 XPA XPB XPC XPD I + PU Synchronous Pulse Transmit (SYPX) PC(1:4).XPC(3:0) = 0000 Together with the values of registers XC(0:1) this signal defines the beginning of time slot 0 at system highway port XDI . The pulse cycle is an integer multiple of 125 µs. SYPX must not be used in parallel with XMFS. I + PU Transmit Multiframe Synchronization (XMFS) PC(1:4).XPC(3:0) = 0001 This port defines the frame and multiframe begin on the transmit system interface ports XDI and XSIG. Depending on PC5.CXMFS the signal on XMFS is active high or low. XMFS must not be used in parallel with SYPX. Note: A new multiframe position has settled at least one multiframe after pulse XMFS has been supplied. I + PU Transmit Signaling Data (XSIG) PC(1:4).XPC(3:0) = 0010 Input for transmit signaling data received from the signaling highway. Optionally, (SIC3.TTRF = 1), sampling of XSIG data is controlled by the active high XSIGM marker. At higher data rates sampling of data is defined by bits SIC2.SICS(2:0). Table 4 Pin Definitions - System Interface (cont’d) Pin No. Ball No. Symbol Input (I) Output (O) Supply (S) Function |
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