PEB2256HT datasheet(85/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

In doubleframe asynchronous state, counting of framing errors, CRC4 bit errors and

detection of remote alarm is stopped. AIS is automatically sent to the backplane interface

(can be disabled by bit FMR2.DAIS). Further on the updating of the registers RSW, RSP,

RSA(8:4), RSA6S and RS(16:1) is halted (remote alarm indication, S

a/Si-bit access).

The multiframe synchronous state is established after detecting two correct multiframe

alignment signals at an interval of n

× 2 ms (n = 1, 2, 3 …). The loss of multiframe

alignment flag FRS0.LMFA is reset. Additionally an interrupt status multiframe alignment

recovery bit ISR2.MFAR is generated with the falling edge of bit FRS0.LMFA.

4.2.3.2

Automatic Force Resynchronization (E1)

In addition, a search for Doubleframe alignment is automatically initiated if two

multiframe pattern with a distance of n

× 2 ms have not been found within a time interval

of 8 ms after doubleframe alignment has been regained (bit FMR1.AFR). A new search

for frame alignment is started just after the previous frame alignment signal.

4.2.3.3

Floating Multiframe Alignment Window (E1)

After reaching doubleframe synchronization a 8 ms timer is started. If a multiframe

alignment signal is found during the 8 ms time interval the internal timer is reset to

remaining 6 ms in order to find the next multiframe signal within this time. If the

multiframe signal is not found for a second time, the interrupt status bit ISR0.T8MS is

set. This interrupt usually occurs every 8 ms until multiframe synchronization is

achieved.

4.2.3.4

CRC4 Performance Monitoring (E1)

In the synchronous state checking of multiframe pattern is disabled. However, with bit

FMR2.ALMF an automatic multiframe resynchronization mode can be activated. If 915

out of 1000 errored CRC submultiframes are found then a false frame alignment is

assumed and a search for doubleframe and multiframe pattern is initiated. The new

search for frame alignment is started just after the previous basic frame alignment signal.

The internal CRC4 resynchronization counter is reset when the multiframe

synchronization has been regained.

4.2.3.5

Modified CRC4 Multiframe Alignment Algorithm (E1)

The modified CRC4 multiframe alignment algorithm allows an automatic interworking

between framers with and without a CRC4 capability. The interworking is realized as it

is described in ITU-T G.706 Appendix B.

If doubleframe synchronization is consistently present but CRC4 multiframe alignment is

not achieved within 400 ms it is assumed that the distant end is initialized to doubleframe

format. The CRC4/non-CRC4 interworking is enabled by FMR2.RFS1/0 = 11 and is

activated only if the receiver has lost its synchronization. If doubleframe alignment (basic

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