PEB2256HT datasheet(98/490 Pages) INFINEON

98 / 490 page

FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

• Clock adaption between system clock (SCLKX) and internally generated transmit

route clock (XCLK).

• Compensation of input wander and jitter.

• Frame alignment between system frame and transmit route frame

• Reporting and controlling of slips

Writing of received data from XDI is controlled by SCLKX/R and SYPX/XMFS in

combination with the programmed offset values for the transmit time slot/clock slot

counters. Reading of stored data is controlled by the clock generated by DCO-X circuitry

or the externally generated TCLK and the transmit framer. With the de-jittered clock data

is read from the transmit elastic buffer and are forwarded to the transmitter. Reporting

and controlling of slips is done according to the receive direction. Positive/negative slips

are reported in interrupt status bits ISR4.XSP and ISR4.XSN. If the transmit buffer is

bypassed data is directly transferred to the transmitter.

The following table gives an overview of the transmit buffer operating modes.

4.4.5

Programmable Pulse Shaper (E1)

The analog transmitter includes a programmable pulse shaper to satisfy the

requirements of ITU-T I.431. The amplitude and shape of the transmit pulses are

completely programmable by registers XPM(2:0).

The transmitter requires an external step up transformer to drive the line.

4.4.6

Transmit Line Monitor (E1)

The transmit line monitor compares the transmit line current on XL1 and XL2 with an on-

chip transmit line current limiter. The monitor detects faults on the primary side of the

transformer indicated by a highly increased transmit line current (more than 120 mA for

at least 3 consecutive pulses sourced by V

DDX

1)) and protects the device from damage

by setting the transmit line driver XL1/2 into high-impedance state automatically (if

enabled by XPM2.DAXLT = 0). The current limiter checks the actual current value of

Table 22

Transmit Buffer Operating Modes (E1)

SIC1.XBS(1:0)

Buffer Size

TS Offset

programming

Slip performance

bypass

enabled

short buffer

enabled

yes

1 frame

enabled

yes

2 frames

enabled

yes

shorts between XL1 or XL2 and V

DDX are not detected

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