PEB2256HT datasheet(102/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

102

2002-08-27

4.5

System Interface in E1 Mode

The FALC56 offers a flexible feature for system designers where for transmit and receive

direction different system clocks and system pulses are necessary. The interface to the

receive system highway is realized by two data buses, one for the data RDO and one for

the signaling data RSIG. The receive highway is clocked on pin SCLKR, while the

interface to the transmit system highway is independently clocked on pin SCLKX. The

frequency of these working clocks and the data rate of 2.048/4.096/8.192/16.384 Mbit/s

for the receive and transmit system interface is programmable by SIC1.SSC1/0, and

SIC1.SSD1, FMR1.SSD0. Selectable system clock and data rates and their valid

combinations are shown in the table below

x = valid, -- = invalid

Generally the data or marker on the system interface are clocked off or latched on the

rising or falling edge (SIC3.RESR/X) of the SCLKR/X clock. Some clocking rates allow

transmission of time slots in different channel phases. Each channel phase which shall

be active on ports RDO, XDI, RP(A:D) and XP(A:D) is programmable by SIC2.SICS(2:0),

the remaining channel phases are cleared or ignored.

The signals on pin SYPR together with the assigned time slot offset in register RC0 and

RC1 define the beginning of a frame on the receive system highway.The signal on pin

SYPX or XMFS together with the assigned time slot offset in register XC0 and XC1

define the beginning of a frame on the transmit system highway.

Adjusting the frame begin (time slot 0, bit 0) relative to SYPR/X or XMFS is possible in

the range of 0 to 125 µs. The minimum shift of varying the time slot 0 begin can be

programmed between 1 bit and 1/8 bit depending of the system clocking and data rate,

e.g. with a clocking/data rate of 2.048 MHz shifting is done bit by bit, while running the

FALC56 with 16.384 MHz and 2.048 Mbit/s data rate it is done by 1/8 bit.

A receive frame marker RFM can be activated during any bit position of the entire frame.

Programming is done with registers RC1/0. The pin function RFM is selected by

PC(4:1).RPC(2:0) = 001. The RFM selection disables the internal time slot assigner, no

offset programming is performed. The receive frame marker is active high for one

Table 23

System Clocking and Data Rates (E1)

System Data Rate

Clock Rate

2.048 MHz

Clock Rate

4.096 MHz

Clock Rate

8.192 MHz

Clock Rate

16.384 MHz

2.048 Mbit/s

4.096 Mbit/s

8.192 Mbit/s

16.384 Mbit/s

PEB2256HT Datasheet(PDF) 102 Page - Infineon Technologies AG

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