PEB2256HT datasheet(49/490 Pages) INFINEON

49 / 490 page

FALC56 V1.2

PEB 2256

Pin Descriptions

Data Sheet

2002-08-27

Note: oD = open drain output

PU = input or input/output comprising an internal pullup device

To override the internal pullup by an external pulldown, a resistor value of 22 k

Ω

is recommended.

The pullup devices are activated during reset, this means their state is undefined

until the reset signal has been applied.

Unused pins containing pullups can be left open.

Unused Pins

N.C.

not connected, to be left open for compatibility

with future products.

Boundary Scan/Joint Test Access Group (JTAG)

TRS

I + PU

Test Reset for Boundary Scan

(active low). If not connected, an internal pullup

transistor ensures high input level.

If the JTAG boundary scan is not used, this pin

must be connected to RES or V

SS.

TDI

I + PU

Test Data Input for Boundary Scan

If not connected an internal pullup transistor

ensures high input level.

TMS

I + PU

Test Mode Select for Boundary Scan

If not connected an internal pullup transistor

ensures high input level.

TCK

I + PU

Test Clock for Boundary Scan

If not connected an internal pullup transistor

ensures high input level.

TDO

Test Data Output for Boundary Scan

Table 5

Pin Definitions - Miscellaneous (cont’d)

No.

Ball

No.

Symbol

Input (I)

Output (O)

Supply (S)

Function

PEB2256HT Datasheet(PDF) 49 Page - Infineon Technologies AG

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