PEB2256HT datasheet(38/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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FALC56 V1.2

PEB 2256

Pin Descriptions

Data Sheet

2002-08-27

RCLK

O + PU

Receive Clock

After reset this port is configured to be

internally pulled up weakly. Setting of bit

PC5.CRP switches this port to be an active

output.

CMR1.RS(1:0) = 00:

Receive clock extracted from the incoming

data pulses. The clock frequency is 2.048 MHz

(E1) or 1.544 MHz (T1/J1). In case of Loss-Of-

Signal (LOS) the RCLK is derived from the

clock that is provided on MCLK.

CMR1.RS(1:0) = 01:

Receive clock extracted from the incoming

data pulses. The clock frequency is 2.048 MHz

(E1) or 1.544 MHz (T1/J1). RCLK remains high

in case of LOS (indicated by FRS0.LOS = 1).

CMR1.RS(1:0) = 10:

Dejittered clock generated by the internal

DCO-R circuit. The clock frequency is

2.048 MHz (E1 or T1/J1 and SIC2.SSC2 = 0)

or 1.544 MHz (T1/J1 and SIC2.SSC2 = 1).

CMR1.RS(1:0) = 11:

Dejittered clock generated by the internal

DCO-R circuit. The clock frequency is

8.192 MHz (E1 or T1/J1 and SIC2.SSC2 = 0)

or 6.176 MHz (T1/J1 and SIC2.SSC2 = 1).

Table 3

Pin Definitions - Clock Generation (cont’d)

No.

Symbol

Input (I)

Output (O)

Supply (S)

Function

PEB2256HT Datasheet(PDF) 38 Page - Infineon Technologies AG

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