PEB2256HT datasheet(74/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

In signaling controller transparent mode, fully transparent data reception without HDLC

framing is performed, i.e. without flag recognition, CRC checking or bit stuffing. This

allows user specific protocol variations.

4.1.14.2

Support of Signaling System #7

The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is

described in ITU-Q.703. The following description assumes, that the reader is familiar

with the SS7 protocol definition.

SS7 support must be activated by setting the MODE register. The SS7 protocol is

supported by the following hardware features in receive mode:

• all Signaling Units (SU) are stored in the receive FIFO (RFIFO)

• detecting of flags from the incoming data stream

• bit stuffing (zero deletion)

• checking of seven or more consecutive ones in the receive data stream

• checking if the received Signaling Unit is a multiple of eight bits and at least six octets

including the opening flag

• calculation of the CRC16 checksum:

In receive direction the calculated checksum is compared to the received one; errors

are reported in register RSIS.

• checking if the signal information field of a received signaling unit consists of more

than 272 octets, in this case the current signaling unit is discarded.

In order to reduce the microprocessor load, fill In signaling units (FISUs) are processed

automatically. By examining the length indicator of a received signal unit the FALC56

decides whether a FISU has been received. Consecutively received FISUs are

compared and optionally not stored in the receive FIFO (RFIFO, 2

×32 bytes), if the

contents is equal to the previous one. The same applies to link status signaling units, if

bit CCR5.CSF is set. The different types of signaling units as message signaling unit

(MSU), link status signaling unit (LSSU) and fill in signaling units (FISU) are indicated in

the RSIS register, which is automatically added to the RFIFO with each received

signaling unit. The complete signaling unit except start and end flags is stored in the

receive FIFO. The functions of bits CCR1.RCRC and CCR1.RADD are still valid in SS7

mode. Errored signaling units are handled automatically according to ITU-T Q.703 as

shown in Figure 20. SU counter (su) and errored SU counter (C

s) are reset by setting

CMDR2.RSUC. The error threshold T can be selected to be 64 (default) or 32 by setting/

clearing bit CCR5.SUET. If the defined error limit is exceeded, an interrupt (ISR1.SUEX)

is generated, if not masked by IMR1.SUEX = 1.

Note: If SUEX is caused by an aborted/invalid frame, the interrupt will be issued

regularly until a valid frame is received (e.g. a FISU).

PEB2256HT Datasheet(PDF) 74 Page - Infineon Technologies AG

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