PEB2256HT datasheet(18/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Introduction

Data Sheet

2002-08-27

Introduction

The FALC56 framer and line interface component is designed to fulfill all required

interfacing between analog E1/T1/J1 lines and the digital PCM system highway,

H.100/H.110 or H-MVIP bus for world market telecommunication systems.

Due to its multitude of implemented functions, it fits to a wide range of networking

applications and fulfills the according international standards. An integrated signaling

controller including Signaling System #7 (SS7) support reduces software overhead.

Crystal-less jitter attenuation with only one master clock source reduces the amount of

required external components.

Equipped with a flexible microprocessor interface, it connects to any control processor

environment. A standard boundary scan interface is provided to support board level

testing. Flat pack or BGA device packaging, minimum number of external components

and low power consumption lead to reduced overall system costs.

Other members of the FALC

® family are the FALC®54 for short-haul applications, the

FALC

®-LH for long-haul and short-haul applications as well as the QuadFALC

supporting four channels on a single chip.

PEB2256HT Datasheet(PDF) 18 Page - Infineon Technologies AG