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WM8962B Datasheet(PDF) 45 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 45 Page - Wolfson Microelectronics plc |
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45 / 295 page ![]() WM8962 Rev 4.3 45 INPUT PGA CONFIGURATION Each of the PGAs operates in a single-ended mode. Configuration of the PGA inputs to the WM8962 input pins is controlled using the register bits shown in Table 6. The maximum available attenuation on any of these input paths is achieved by using register bits shown in Table 6 to disconnect the input pins from the applicable PGA. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R37 (25h) Left input PGA control 3 IN1L_TO_INPGAL 1 Selects the IN1L pin as an input to the Left PGA 0 = Disabled 1 = Enabled 2 IN2L_TO_INPGAL 0 Selects the IN2L pin as an input to the Left PGA 0 = Disabled 1 = Enabled 1 IN3L_TO_INPGAL 0 Selects the IN3L pin as an input to the Left PGA 0 = Disabled 1 = Enabled 0 IN4L_TO_INPGAL 0 Selects the IN4L pin as an input to the Left PGA 0 = Disabled 1 = Enabled R38 (26h) Right input PGA control 3 IN1R_TO_INPGA R 1 Selects the IN1R pin as an input to the Right PGA 0 = Disabled 1 = Enabled 2 IN2R_TO_INPGA R 0 Selects the IN2R pin as an input to the Right PGA 0 = Disabled 1 = Enabled 1 IN3R_TO_INPGA R 0 Selects the IN3R pin as an input to the Right PGA 0 = Disabled 1 = Enabled 0 IN4R_TO_INPGA R 0 Selects the IN4R pin as an input to the Right PGA 0 = Disabled 1 = Enabled Table 6 Input PGA Configuration |
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