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WM8962B Datasheet(PDF) 28 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 28 Page - Wolfson Microelectronics plc |
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28 / 295 page  WM8962 28 Rev 4.3 DIGITAL AUDIO INTERFACE - SLAVE MODE BCLK (input) LRCLK (input) ADCDAT (output) DACDAT (input) tDS tDD tDH tLRH tLRSU tBCH tBCL tBCY Figure 4 Audio Interface Timing – Slave Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Slave Mode BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 16 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 14 ns DACDAT set-up time to BCLK rising edge tDS 10 ns Note: BCLK period should always be greater than or equal to MCLK period. |
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