WM8962B datasheet(63/295 Pages) WOLFSON

63 / 295 page

WM8962

Rev 4.3

DIGITAL MICROPHONE INTERFACE

The WM8962 supports a stereo digital microphone interface. Two channels of audio data are

multiplexed on a GPIO pin configured for digital microphone input.

The digital microphone data input (DMICDAT) is provided on GPIO5 or GPIO6 by setting the

respective GPn_FN register to 1_0100. The associated clock (DMICCLK) is provided on a separate

GPIO pin by setting the respective

GPn_FN register to 1_0011. See “General Purpose Input/Output

(GPIO)

” section for details on these registers.

Note that care must be taken to ensure that the respective digital logic levels of the microphone are

compatible with the digital input thresholds of the WM8962. The digital input thresholds are referenced

to DBVDD, as defined in “Electrical Characteristics”. It is recommended to power the digital

microphones from DBVDD.

When digital microphone input is enabled, the WM8962 outputs a clock signal (DMICCLK) on the

Digital Microphone Clock Output pin (this must be configured on one of the GPIO pins). The clock

frequency for all supported digital microphone clocking modes is described later in this section.

A pair of digital microphones is connected as illustrated in Figure 21. The microphones must be

configured to ensure that the Left mic transmits a data bit when DMICCLK is high, and the Right mic

transmits a data bit when DMICCLK is low. The WM8962 samples the digital microphone data at the

end of each DMICCLK phase. Each microphone must tri-state its data output when the other

microphone is transmitting.

Digital Mic

DMICDAT

0.1uF

DBVDD

DGND

Digital Mic

DMICCLK

VDD

CLK

DATA

VDD

CLK

DATA

CHAN

VDD

Digital

Microphone

Interface

DMICCLK is available on GPIO2, GPIO3, GPIO5 and GPIO6

DMICDAT is supported on GPIO5 and GPIO6

Figure 21 Digital Microphone Input

The digital microphone signal paths are enabled using the DMIC_ENA register. When DMIC_ENA is

set, the ADC path is disconnected and the digital microphone data is routed to the digital core, as

illustrated in “Digital Mixing”.

Two microphone channels are interleaved on DMICDAT; the timing is illustrated in Figure 22. Each

microphone must tri-state its data output when the other microphone is transmitting.

WM8962B Datasheet(PDF) 63 Page - Wolfson Microelectronics plc

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