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AS4C64M32MD2-25BCN Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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AS4C64M32MD2-25BCN Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
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2 / 129 page ![]() KEY FEATURE •Double-data rate architecture; two data transfers per clock cycle • Bidirectional data strobes (DQS, DQS#), These are transmitted/received with data to be used in capturing data at the receiver • Differential clock inputs (CK and CK#) • Differential data strobes (DQS and DQS#) • Commands & addresses entered on both positive and negative CK edges; data and data mask referenced to both edges of DQS • 8 internal banks for concurrent operation • Data mask (DM) for write data • Burst Length: 4 (default), 8 or 16 • Burst Type: Sequential or Interleave • Read & Write latency : Refer to Table 51 LPDDR2 AC Timing Table • Auto Precharge option for each burst access • Configurable Drive Strength • Auto Refresh and Self Refresh Modes • Partial Array Self Refresh and Temperature Compensated Self Refresh • Deep Power Down Mode • HSUL_12 compatible inputs • VDD1/VDD2/VDDQ/VDDCA : 1.8V/1.2V/1.2V/1.2V • No DLL : CK to DQS is not synchronized • Edge aligned data output, center aligned data input • Operating Temperature : - 30 to 85 °C • Auto refresh duty cycle : 3.9us • Package type : 134-ball FBGA 10x11.5x1.0mm (max) Table1.OrderingInformation PartNumber Org Temperature MaxClock(MHz) Package AS4C 128M16MD2-25BCN 128Mx16 Commercial -30°Cto+85°C 400 134-ballFBGA Table2.SpeedGradeInformation AS4C 64M32MD2-25BCN 64Mx32 Commercial -30°Cto+85°C 400 134-ballFBGA AS4C64M32MD2-25BCN AS4C128M16MD2-25BCN Confidential - 2/129 - Rev.1.0 July 2016 SpeedGrade ClockFrequency RL tRCD(ns) tRP(ns) DDR2 L-800 400MHz 6 1 8 1 8 WL 3 |
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